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| author | Sonic Zhang <sonic.zhang@analog.com> | 2010-11-16 09:41:07 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-01-10 07:18:22 -0500 |
| commit | 84e97c1014a2afe1a07beb1b6de5f2d867b368fd (patch) | |
| tree | fc5bd785faa3055c6de6a1d0ccad911923ad6df8 /arch/blackfin | |
| parent | 503f3d30c6f29c58fce77bfe47b04e3c667e7640 (diff) | |
| download | linux-84e97c1014a2afe1a07beb1b6de5f2d867b368fd.tar.gz linux-84e97c1014a2afe1a07beb1b6de5f2d867b368fd.tar.bz2 linux-84e97c1014a2afe1a07beb1b6de5f2d867b368fd.zip | |
Blackfin: SMP: kgdb: apply anomaly 257 work around
When run kgdb testing, it looks like coreb hangs in single step or trap
exception without handling anomaly 05000257 properly on bf561 v0.5. But,
the anomaly list says it apply to bf561 v0.4 and bellow. Apply its work
around to 0.5 temporarily until the behavior and the root cause can be
confirmed by the hardware team.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/anomaly.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index 4c108c99cb6e..6a3499b02097 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h @@ -181,7 +181,11 @@ /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ #define ANOMALY_05000254 (__SILICON_REVISION__ > 3) /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ -#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) +/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception + * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change + * after the behavior and the root cause are confirmed with hardware team. + */ +#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP)) /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ #define ANOMALY_05000258 (__SILICON_REVISION__ < 5) /* ICPLB_STATUS MMR Register May Be Corrupted */ |