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| author | Guo Ren <guoren@linux.alibaba.com> | 2020-01-31 20:33:10 +0800 |
|---|---|---|
| committer | Guo Ren <guoren@linux.alibaba.com> | 2020-02-21 15:43:24 +0800 |
| commit | 997153b9a75c08d545ad45e6f8ceb432435d2425 (patch) | |
| tree | 830915f73d05e7d094d2f293a712e05c0da1e6f5 /arch/csky/include/asm | |
| parent | cc1f6563a92ced0889775d0587316d725b6e1a68 (diff) | |
| download | linux-997153b9a75c08d545ad45e6f8ceb432435d2425.tar.gz linux-997153b9a75c08d545ad45e6f8ceb432435d2425.tar.bz2 linux-997153b9a75c08d545ad45e6f8ceb432435d2425.zip | |
csky: Add flush_icache_mm to defer flush icache all
Some CPUs don't support icache.va instruction to maintain the whole
smp cores' icache. Using icache.all + IPI casue a lot on performace
and using defer mechanism could reduce the number of calling icache
_flush_all functions.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Diffstat (limited to 'arch/csky/include/asm')
| -rw-r--r-- | arch/csky/include/asm/cacheflush.h | 1 | ||||
| -rw-r--r-- | arch/csky/include/asm/mmu.h | 1 | ||||
| -rw-r--r-- | arch/csky/include/asm/mmu_context.h | 2 |
3 files changed, 4 insertions, 0 deletions
diff --git a/arch/csky/include/asm/cacheflush.h b/arch/csky/include/asm/cacheflush.h index a96da67261ae..f0b8f25429a2 100644 --- a/arch/csky/include/asm/cacheflush.h +++ b/arch/csky/include/asm/cacheflush.h @@ -4,6 +4,7 @@ #ifndef __ASM_CSKY_CACHEFLUSH_H #define __ASM_CSKY_CACHEFLUSH_H +#include <linux/mm.h> #include <abi/cacheflush.h> #endif /* __ASM_CSKY_CACHEFLUSH_H */ diff --git a/arch/csky/include/asm/mmu.h b/arch/csky/include/asm/mmu.h index b382a14ea4ec..26fbb1d15df0 100644 --- a/arch/csky/include/asm/mmu.h +++ b/arch/csky/include/asm/mmu.h @@ -7,6 +7,7 @@ typedef struct { atomic64_t asid; void *vdso; + cpumask_t icache_stale_mask; } mm_context_t; #endif /* __ASM_CSKY_MMU_H */ diff --git a/arch/csky/include/asm/mmu_context.h b/arch/csky/include/asm/mmu_context.h index 0285b0ad18b6..abdf1f1cb6ec 100644 --- a/arch/csky/include/asm/mmu_context.h +++ b/arch/csky/include/asm/mmu_context.h @@ -43,5 +43,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, TLBMISS_HANDLER_SETUP_PGD(next->pgd); write_mmu_entryhi(next->context.asid.counter); + + flush_icache_deferred(next); } #endif /* __ASM_CSKY_MMU_CONTEXT_H */ |