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| author | Huacai Chen <chenhuacai@loongson.cn> | 2023-06-29 20:58:44 +0800 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2023-06-29 20:58:44 +0800 |
| commit | 01158487af60cd3915e8c31924144caf29cb0767 (patch) | |
| tree | 01bdd88063128e646a6fdc394a9c2d8c7a138316 /arch/loongarch/include/asm/cpu-features.h | |
| parent | e031a5f3f1eddb961a6ded8a21ab8189d8760860 (diff) | |
| download | linux-01158487af60cd3915e8c31924144caf29cb0767.tar.gz linux-01158487af60cd3915e8c31924144caf29cb0767.tar.bz2 linux-01158487af60cd3915e8c31924144caf29cb0767.zip | |
LoongArch: Introduce hardware page table walker
Loongson-3A6000 and newer processors have hardware page table walker
(PTW) support. PTW can handle all fastpaths of TLBI/TLBL/TLBS/TLBM
exceptions by hardware, software only need to handle slowpaths (page
faults).
BTW, PTW doesn't append _PAGE_MODIFIED for page table entries, so we
change pmd_dirty() and pte_dirty() to also check _PAGE_DIRTY for the
"dirty" attribute.
Signed-off-by: Liang Gao <gaoliang@loongson.cn>
Signed-off-by: Jun Yi <yijun@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/include/asm/cpu-features.h')
| -rw-r--r-- | arch/loongarch/include/asm/cpu-features.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/include/asm/cpu-features.h index f6177f133477..2eafe6a6aca8 100644 --- a/arch/loongarch/include/asm/cpu-features.h +++ b/arch/loongarch/include/asm/cpu-features.h @@ -64,6 +64,6 @@ #define cpu_has_eiodecode cpu_opt(LOONGARCH_CPU_EIODECODE) #define cpu_has_guestid cpu_opt(LOONGARCH_CPU_GUESTID) #define cpu_has_hypervisor cpu_opt(LOONGARCH_CPU_HYPERVISOR) - +#define cpu_has_ptw cpu_opt(LOONGARCH_CPU_PTW) #endif /* __ASM_CPU_FEATURES_H */ |