diff options
author | Greg Ungerer <gerg@uclinux.org> | 2012-07-15 21:42:47 +1000 |
---|---|---|
committer | Greg Ungerer <gerg@uclinux.org> | 2012-09-27 23:33:46 +1000 |
commit | 6a3a786d02172b34d0ffba6f80bd1150da51125d (patch) | |
tree | 30ea2e51ba71f9a2adf987d38cc015294a53300a /arch/m68k/include/asm/m5206sim.h | |
parent | 300b9ff609ca027b9964a453a8156e6fe0077cde (diff) | |
download | linux-6a3a786d02172b34d0ffba6f80bd1150da51125d.tar.gz linux-6a3a786d02172b34d0ffba6f80bd1150da51125d.tar.bz2 linux-6a3a786d02172b34d0ffba6f80bd1150da51125d.zip |
m68knommu: make ColdFire IMR and IPR register definitions absolute addresses
Make all definitions of the ColdFire Interrupt Mask and Pending registers
absolute addresses. Currently some are relative to the MBAR peripheral region.
The various ColdFire parts use different methods to address the internal
registers, some are absolute, some are relative to peripheral regions
which can be mapped at different address ranges (such as the MBAR and IPSBAR
registers). We don't want to deal with this in the code when we are
accessing these registers, so make all register definitions the absolute
address - factoring out whether it is an offset into a peripheral region.
This makes them all consistently defined, and reduces the occasional bugs
caused by inconsistent definition of the register addresses.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m5206sim.h')
-rw-r--r-- | arch/m68k/include/asm/m5206sim.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index 69722366b084..e8bae33aed60 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h @@ -40,8 +40,8 @@ #define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */ #endif -#define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */ -#define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */ +#define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */ +#define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */ #define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */ #define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/ |