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author | Greg Ungerer <gerg@uclinux.org> | 2011-03-06 23:01:46 +1000 |
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committer | Greg Ungerer <gerg@uclinux.org> | 2011-03-15 21:01:55 +1000 |
commit | 6a92e1982d5c538d1cfafbe4b0cb16d49306854f (patch) | |
tree | 700847577d3cd3385125fe46822e8759a76607da /arch/m68k/include/asm/m5249sim.h | |
parent | 58f0ac98f386d2b335e5852e8feec828c43a0e13 (diff) | |
download | linux-6a92e1982d5c538d1cfafbe4b0cb16d49306854f.tar.gz linux-6a92e1982d5c538d1cfafbe4b0cb16d49306854f.tar.bz2 linux-6a92e1982d5c538d1cfafbe4b0cb16d49306854f.zip |
m68knommu: clean up use of MBAR for DRAM registers on ColdFire start
In some of the RAM size autodetection code on ColdFire CPU startup
we reference DRAM registers relative to the MBAR register. Not all of
the supported ColdFire CPUs have an MBAR, and currently this works
because we fake an MBAR address on those registers. In an effort to
clean this up, and eventually remove the fake MBAR setting make the
DRAM register address definitions actually contain the MBAR (or IPSBAR
as appropriate) value as required.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m5249sim.h')
-rw-r--r-- | arch/m68k/include/asm/m5249sim.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index c318ce786f93..33b0b4df07ca 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -60,11 +60,11 @@ #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ +#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ +#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ +#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */ +#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */ /* * Timer module. |