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| author | Sergey Ryazanov <ryazanov.s.a@gmail.com> | 2014-10-29 03:18:45 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-11-24 07:45:28 +0100 |
| commit | 1654861f6e02e74a2ba059d1f62dc0356429d7cf (patch) | |
| tree | 06ca7f47a494bf1e24bd186e2b82a95d1e2ced25 /arch/mips/ath25/ar5312.c | |
| parent | a7473717483ef3bb78563611bf1b3b82c5515b2e (diff) | |
| download | linux-1654861f6e02e74a2ba059d1f62dc0356429d7cf.tar.gz linux-1654861f6e02e74a2ba059d1f62dc0356429d7cf.tar.bz2 linux-1654861f6e02e74a2ba059d1f62dc0356429d7cf.zip | |
MIPS: ath25: add SoC type detection
Detect SoC type based on device ID and board configuration data.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Linux MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8244/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ath25/ar5312.c')
| -rw-r--r-- | arch/mips/ath25/ar5312.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/mips/ath25/ar5312.c b/arch/mips/ath25/ar5312.c index 41bd56d6ab23..26942a2c298d 100644 --- a/arch/mips/ath25/ar5312.c +++ b/arch/mips/ath25/ar5312.c @@ -24,6 +24,8 @@ #include <asm/reboot.h> #include <asm/time.h> +#include <ath25_platform.h> + #include "devices.h" #include "ar5312.h" #include "ar5312_regs.h" @@ -191,10 +193,25 @@ static void __init ar5312_flash_init(void) void __init ar5312_init_devices(void) { + struct ath25_boarddata *config; + ar5312_flash_init(); /* Locate board/radio config data */ ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE); + config = ath25_board.config; + + /* AR2313 has CPU minor rev. 10 */ + if ((current_cpu_data.processor_id & 0xff) == 0x0a) + ath25_soc = ATH25_SOC_AR2313; + + /* AR2312 shares the same Silicon ID as AR5312 */ + else if (config->flags & BD_ISCASPER) + ath25_soc = ATH25_SOC_AR2312; + + /* Everything else is probably AR5312 or compatible */ + else + ath25_soc = ATH25_SOC_AR5312; } static void ar5312_restart(char *command) @@ -282,6 +299,7 @@ void __init ar5312_plat_mem_setup(void) { void __iomem *sdram_base; u32 memsize, memcfg, bank0_ac, bank1_ac; + u32 devid; /* Detect memory size */ sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE, @@ -297,6 +315,11 @@ void __init ar5312_plat_mem_setup(void) ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE); + devid = ar5312_rst_reg_read(AR5312_REV); + devid >>= AR5312_REV_WMAC_MIN_S; + devid &= AR5312_REV_CHIP; + ath25_board.devid = (u16)devid; + /* Clear any lingering AHB errors */ ar5312_rst_reg_read(AR5312_PROCADDR); ar5312_rst_reg_read(AR5312_DMAADDR); |