diff options
author | Joshua Kinard <kumba@gentoo.org> | 2017-11-18 23:00:51 -0500 |
---|---|---|
committer | Paul Burton <paul.burton@mips.com> | 2018-07-12 11:25:25 -0700 |
commit | 4936084c2ee227524c242d790a9fbad7650320c7 (patch) | |
tree | 153449026d2682524d9e43d03aa05e3caf2ff3ac /arch/mips/ath79 | |
parent | a0a5ac3ce8fe6bf26694f49f9ba42ed859487424 (diff) | |
download | linux-4936084c2ee227524c242d790a9fbad7650320c7.tar.gz linux-4936084c2ee227524c242d790a9fbad7650320c7.tar.bz2 linux-4936084c2ee227524c242d790a9fbad7650320c7.zip |
MIPS: Cleanup R10000_LLSC_WAR logic in atomic.h
This patch reduces down the conditionals in MIPS atomic code that deal
with a silicon bug in early R10000 cpus that required a workaround of
a branch-likely instruction following a store-conditional in order to
to guarantee the whole ll/sc sequence is atomic. As the only real
difference is a branch-likely instruction (beqzl) over a standard
branch (beqz), the conditional is reduced down to a single preprocessor
check at the top to pick the required instruction.
This requires writing the uses in assembler, thus we discard the
non-R10000 case that uses a mixture of a C do...while loop with
embedded assembler that was added back in commit 7837314d141c ("MIPS:
Get rid of branches to .subsections."). A note found in the git log
for commit 5999eca25c1f ("[MIPS] Improve branch prediction in ll/sc
atomic operations.") is also addressed.
The macro definition for the branch instruction and the code comment
derives from a patch sent in earlier by Paul Burton for various cmpxchg
cleanups.
[paul.burton@mips.com:
- Minor whitespace fix for checkpatch.]
Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/17736/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <james.hogan@mips.com>
Cc: "Maciej W. Rozycki" <macro@mips.com>
Cc: linux-mips@linux-mips.org
Diffstat (limited to 'arch/mips/ath79')
0 files changed, 0 insertions, 0 deletions