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| author | Aaro Koskinen <aaro.koskinen@iki.fi> | 2013-06-23 20:38:44 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-07-01 15:10:56 +0200 |
| commit | a135a9b5d9683ace787c7d86f1e642d9acfacdde (patch) | |
| tree | 2965c7e97a65f81adbce72ce98d3df230213dcc8 /arch/mips/cavium-octeon/executive | |
| parent | 6ba045f9fbdafb48da42aa8576ea7a3980443136 (diff) | |
| download | linux-a135a9b5d9683ace787c7d86f1e642d9acfacdde.tar.gz linux-a135a9b5d9683ace787c7d86f1e642d9acfacdde.tar.bz2 linux-a135a9b5d9683ace787c7d86f1e642d9acfacdde.zip | |
MIPS: Octeon: Enable interfaces on EdgeRouter Lite
Enable interfaces on EdgeRouter Lite. Tested with cavium_octeon_defconfig
and busybox shell. DHCP & ping works with eth0, eth1 and eth2.
The board type "UBNT_E100" is taken from the sources of the vendor kernel
shipped with the product.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Acked-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5546/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/cavium-octeon/executive')
| -rw-r--r-- | arch/mips/cavium-octeon/executive/cvmx-helper-board.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c index 7c6497781895..0a1283ce47f5 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c @@ -181,6 +181,11 @@ int cvmx_helper_board_get_mii_address(int ipd_port) return ipd_port - 16 + 4; else return -1; + case CVMX_BOARD_TYPE_UBNT_E100: + if (ipd_port >= 0 && ipd_port <= 2) + return 7 - ipd_port; + else + return -1; } /* Some unknown board. Somebody forgot to update this function... */ @@ -706,6 +711,14 @@ int __cvmx_helper_board_hardware_enable(int interface) } } } + } else if (cvmx_sysinfo_get()->board_type == + CVMX_BOARD_TYPE_UBNT_E100) { + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0); + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0x10); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0x10); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(2, interface), 0); + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(2, interface), 0x10); } return 0; } |