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| author | James Hogan <james.hogan@imgtec.com> | 2016-12-07 17:16:37 +0000 |
|---|---|---|
| committer | James Hogan <james.hogan@imgtec.com> | 2017-02-03 15:21:32 +0000 |
| commit | 013044cc65f8661c5fa2b59da5e134b3453d975d (patch) | |
| tree | 801ef5a0bad1220d2d1b6fc271e11dfaf5e7d9bd /arch/mips/include | |
| parent | be67a0be94b65746dee63af5c184c78d00a707f6 (diff) | |
| download | linux-013044cc65f8661c5fa2b59da5e134b3453d975d.tar.gz linux-013044cc65f8661c5fa2b59da5e134b3453d975d.tar.bz2 linux-013044cc65f8661c5fa2b59da5e134b3453d975d.zip | |
KVM: MIPS/T&E: Expose CP0_EntryLo0/1 registers
Expose the CP0_EntryLo0 and CP0_EntryLo1 registers through the KVM
register access API. This is fairly straightforward for trap & emulate
since we don't support the RI and XI bits. For the sake of future
proofing (particularly for VZ) it is explicitly specified that the API
always exposes the 64-bit version of these registers (i.e. with the RI
and XI bits in bit positions 63 and 62 respectively), and they are
implemented in trap_emul.c rather than mips.c to allow them to be
implemented differently for VZ.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/kvm_host.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index 420372fa5bbc..66459ca4af81 100644 --- a/arch/mips/include/asm/kvm_host.h +++ b/arch/mips/include/asm/kvm_host.h @@ -352,7 +352,9 @@ struct kvm_vcpu_arch { #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0]) #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val) #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0]) +#define kvm_write_c0_guest_entrylo0(cop0, val) (cop0->reg[MIPS_CP0_TLB_LO0][0] = (val)) #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0]) +#define kvm_write_c0_guest_entrylo1(cop0, val) (cop0->reg[MIPS_CP0_TLB_LO1][0] = (val)) #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0]) #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val)) #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2]) |