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authorPaul Burton <paul.burton@imgtec.com>2017-06-09 17:26:39 -0700
committerRalf Baechle <ralf@linux-mips.org>2017-06-29 02:42:25 +0200
commitb70eb30056dc84568f3d32440d9be6a558025843 (patch)
tree2e0ab36189d3eb6dbf5bbb995b9aa7bf896a6e0f /arch/mips/include
parent8263db4d7768448cb06adbbdd14c613a1ea09830 (diff)
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MIPS: cmpxchg: Implement 1 byte & 2 byte xchg()
Implement 1 & 2 byte xchg() using read-modify-write atop a 4 byte cmpxchg(). This allows us to support these atomic operations despite the MIPS ISA only providing for 4 & 8 byte atomic operations. This is required in order to support queued spinlocks (qspinlock) in a later patch, since these make use of a 2 byte xchg() in their slow path. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16354/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/cmpxchg.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 516cb66f066b..a633bf845689 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -70,9 +70,16 @@ extern unsigned long __xchg_called_with_bad_pointer(void)
__ret; \
})
+extern unsigned long __xchg_small(volatile void *ptr, unsigned long val,
+ unsigned int size);
+
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
switch (size) {
+ case 1:
+ case 2:
+ return __xchg_small(ptr, x, size);
+
case 4:
return __xchg_asm("ll", "sc", (volatile u32 *)ptr, x);
@@ -91,8 +98,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
({ \
__typeof__(*(ptr)) __res; \
\
- BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
- \
smp_mb__before_llsc(); \
\
__res = (__typeof__(*(ptr))) \