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| author | WANG Xuerui <git@xen0n.name> | 2020-07-29 21:14:15 +0800 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-07-31 17:52:10 +0200 |
| commit | efd1b4ad3d5178a74387bc5ff69a2d4585f586c6 (patch) | |
| tree | 820e92edafd43538e37075f9a19c78a563302a16 /arch/mips/kernel/traps.c | |
| parent | 48f5dd56cf2980ff932c6fd98ff5a2c503cde97b (diff) | |
| download | linux-efd1b4ad3d5178a74387bc5ff69a2d4585f586c6.tar.gz linux-efd1b4ad3d5178a74387bc5ff69a2d4585f586c6.tar.bz2 linux-efd1b4ad3d5178a74387bc5ff69a2d4585f586c6.zip | |
MIPS: only register FTLBPar exception handler for supported models
Previously ExcCode 16 is unconditionally treated as the FTLB parity
exception (FTLBPar), but in fact its semantic is implementation-
dependent. Looking at various manuals it seems the FTLBPar exception is
only present on some recent MIPS Technologies cores, so only register
the handler on these.
Fixes: 75b5b5e0a262790f ("MIPS: Add support for FTLBs")
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Cc: Paul Burton <paulburton@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/kernel/traps.c')
| -rw-r--r-- | arch/mips/kernel/traps.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 06aba49d37c9..9c37a6997259 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2454,7 +2454,8 @@ void __init trap_init(void) if (cpu_has_fpu && !cpu_has_nofpuex) set_except_vector(EXCCODE_FPE, handle_fpe); - set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb); + if (cpu_has_ftlbparex) + set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb); if (cpu_has_rixiex) { set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0); |