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| author | Stafford Horne <shorne@gmail.com> | 2017-07-07 06:06:30 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-11-03 14:01:16 +0900 |
| commit | 4553474d977d1ee8a81067cfbc588f1df84ce3e9 (patch) | |
| tree | 4e74260eb9134fd94a7bc20fc3ab23e4ecb3a7e1 /arch/openrisc/kernel/smp.c | |
| parent | 78cdfb5cf15e0f9fb4c2a9176a13a907a1d024f0 (diff) | |
| download | linux-4553474d977d1ee8a81067cfbc588f1df84ce3e9.tar.gz linux-4553474d977d1ee8a81067cfbc588f1df84ce3e9.tar.bz2 linux-4553474d977d1ee8a81067cfbc588f1df84ce3e9.zip | |
openrisc: add tick timer multi-core sync logic
In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu. This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.
This synchronization routine heavily borrows from mips implementation that
does something similar.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'arch/openrisc/kernel/smp.c')
| -rw-r--r-- | arch/openrisc/kernel/smp.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c index 4763b8b9161e..4d80ce6fa045 100644 --- a/arch/openrisc/kernel/smp.c +++ b/arch/openrisc/kernel/smp.c @@ -100,6 +100,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) pr_crit("CPU%u: failed to start\n", cpu); return -EIO; } + synchronise_count_master(cpu); return 0; } @@ -129,6 +130,8 @@ asmlinkage __init void secondary_start_kernel(void) set_cpu_online(cpu, true); complete(&cpu_running); + synchronise_count_slave(cpu); + local_irq_enable(); preempt_disable(); |