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| author | Alessio Igor Bogani <alessio.bogani@elettra.eu> | 2016-05-30 11:47:16 +0200 |
|---|---|---|
| committer | Scott Wood <oss@buserror.net> | 2016-07-08 20:01:27 -0500 |
| commit | 97493e2e9eeddfecaca741454f97a689d8141dcf (patch) | |
| tree | f025cf7b2151a8dee405eafa1d3f31f13d8cff92 /arch/powerpc/boot/ppcboot.h | |
| parent | ae9ac1d3299ab8334f0b5293ddb77e18f2a9c9e5 (diff) | |
| download | linux-97493e2e9eeddfecaca741454f97a689d8141dcf.tar.gz linux-97493e2e9eeddfecaca741454f97a689d8141dcf.tar.bz2 linux-97493e2e9eeddfecaca741454f97a689d8141dcf.zip | |
powerpc/86xx: Add support for Emerson/Artesyn MVME7100
Add support for the Artesyn MVME7100 Single Board Computer.
The MVME7100 is a 6U form factor VME64 computer with:
- A two e600 cores Freescale MPC8641D CPU
- 2 GB of DDR2 onboard memory
- Four Gigabit Ethernets
- Five 16550 compatible UARTs
- One USB 2.0 port
- Two PCI/PCI eXpress Mezzanine Card (PMC/XMC) Slots
- A DS1375 Real Time Clock (RTC)
- 512 KB of Non-Volatile Memory (NVRAM)
- Two 64 KB EEPROMs
- 128 MB NOR and 4/8 GB NAND Flash
This patch is based on linux-4.7-rc1 and has been only boot tested.
Limitations:
This patch covers only models 171 and 173
No plans to support CPLD timers
Know issues:
All four PHYs work in polling mode
Configuration is missing for:
PCI IDSEL and PCI Interrupt definition
Support is missing for:
Cache and memory controllers (which are very similar to the 85xx ones
but right now I don't know if we can re-use their support)
Watchdog, USB, NVRAM, NOR, NAND, EEPROMs, VME, PMC/XMC and RTC
Signed-off-by: Alessio Igor Bogani <alessio.bogani@elettra.eu>
Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'arch/powerpc/boot/ppcboot.h')
| -rw-r--r-- | arch/powerpc/boot/ppcboot.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/boot/ppcboot.h b/arch/powerpc/boot/ppcboot.h index 6ae6f9063952..453df429d5d0 100644 --- a/arch/powerpc/boot/ppcboot.h +++ b/arch/powerpc/boot/ppcboot.h @@ -43,7 +43,7 @@ typedef struct bd_info { unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ #if defined(TARGET_8xx) || defined(TARGET_CPM2) || defined(TARGET_85xx) ||\ - defined(TARGET_83xx) + defined(TARGET_83xx) || defined(TARGET_86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif #if defined(TARGET_PPC_MPC52xx) |