summaryrefslogtreecommitdiffstats
path: root/arch/powerpc/kernel/cpu_setup_44x.S
diff options
context:
space:
mode:
authorValentine Barshak <vbarshak@ru.mvista.com>2007-09-22 00:50:09 +1000
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2007-10-03 07:20:18 -0500
commit340ffd267c85fc28da7cfd681b177c816af800cf (patch)
treeb9a757d6d0566420fe103c02d60f2b520e5c3880 /arch/powerpc/kernel/cpu_setup_44x.S
parent8112753bb2c0045398c89d0647792b39805f6d40 (diff)
downloadlinux-340ffd267c85fc28da7cfd681b177c816af800cf.tar.gz
linux-340ffd267c85fc28da7cfd681b177c816af800cf.tar.bz2
linux-340ffd267c85fc28da7cfd681b177c816af800cf.zip
[POWERPC] 4xx: 440EPx/GRx incorrect write to DDR SDRAM errata workaround
Add a workaround for PowerPC 440EPx/GRx incorrect write to DDR SDRAM errata. Data can be written to wrong address in SDRAM when write pipelining enabled on plb0. We disable it in the cpu_setup for these processors at early init. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/kernel/cpu_setup_44x.S')
-rw-r--r--arch/powerpc/kernel/cpu_setup_44x.S25
1 files changed, 24 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_44x.S b/arch/powerpc/kernel/cpu_setup_44x.S
index c790634d946b..8e1812e2f3ee 100644
--- a/arch/powerpc/kernel/cpu_setup_44x.S
+++ b/arch/powerpc/kernel/cpu_setup_44x.S
@@ -20,7 +20,14 @@
_GLOBAL(__setup_cpu_440ep)
b __init_fpu_44x
_GLOBAL(__setup_cpu_440epx)
- b __init_fpu_44x
+ mflr r4
+ bl __init_fpu_44x
+ bl __plb_disable_wrp
+ mtlr r4
+ blr
+_GLOBAL(__setup_cpu_440grx)
+ b __plb_disable_wrp
+
/* enable APU between CPU and FPU */
_GLOBAL(__init_fpu_44x)
@@ -31,3 +38,19 @@ _GLOBAL(__init_fpu_44x)
isync
blr
+/*
+ * Workaround for the incorrect write to DDR SDRAM errata.
+ * The write address can be corrupted during writes to
+ * DDR SDRAM when write pipelining is enabled on PLB0.
+ * Disable write pipelining here.
+ */
+#define DCRN_PLB4A0_ACR 0x81
+
+_GLOBAL(__plb_disable_wrp)
+ mfdcr r3,DCRN_PLB4A0_ACR
+ /* clear WRP bit in PLB4A0_ACR */
+ rlwinm r3,r3,0,8,6
+ mtdcr DCRN_PLB4A0_ACR,r3
+ isync
+ blr
+