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| author | Christophe Leroy <christophe.leroy@c-s.fr> | 2019-05-14 09:05:13 +0000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2019-07-05 01:35:10 +1000 |
| commit | 1cfb725fb1899dc6fdc88f8b5354a65e8ad260c6 (patch) | |
| tree | 1e1a4bf185f110b05a2f47b7ed9533d3893d81d1 /arch/powerpc/kernel | |
| parent | 6c5875843b87c3adea2beade9d1b8b3d4523900a (diff) | |
| download | linux-1cfb725fb1899dc6fdc88f8b5354a65e8ad260c6.tar.gz linux-1cfb725fb1899dc6fdc88f8b5354a65e8ad260c6.tar.bz2 linux-1cfb725fb1899dc6fdc88f8b5354a65e8ad260c6.zip | |
powerpc/64: flush_inval_dcache_range() becomes flush_dcache_range()
On most arches having function flush_dcache_range(), including PPC32,
this function does a writeback and invalidation of the cache bloc.
On PPC64, flush_dcache_range() only does a writeback while
flush_inval_dcache_range() does the invalidation in addition.
In addition it looks like within arch/powerpc/, there are no PPC64
platforms using flush_dcache_range()
This patch drops the existing 64 bits version of flush_dcache_range()
and renames flush_inval_dcache_range() into flush_dcache_range().
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/kernel')
| -rw-r--r-- | arch/powerpc/kernel/misc_64.S | 27 |
1 files changed, 2 insertions, 25 deletions
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S index 262ba9481781..a4fd536efb44 100644 --- a/arch/powerpc/kernel/misc_64.S +++ b/arch/powerpc/kernel/misc_64.S @@ -121,31 +121,8 @@ EXPORT_SYMBOL(flush_icache_range) * * flush all bytes from start to stop-1 inclusive */ -_GLOBAL_TOC(flush_dcache_range) -/* - * Flush the data cache to memory - * - * Different systems have different cache line sizes - */ - ld r10,PPC64_CACHES@toc(r2) - lwz r7,DCACHEL1BLOCKSIZE(r10) /* Get dcache block size */ - addi r5,r7,-1 - andc r6,r3,r5 /* round low to line bdy */ - subf r8,r6,r4 /* compute length */ - add r8,r8,r5 /* ensure we get enough */ - lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of dcache block size */ - srw. r8,r8,r9 /* compute line count */ - beqlr /* nothing to do? */ - mtctr r8 -0: dcbst 0,r6 - add r6,r6,r7 - bdnz 0b - sync - blr -EXPORT_SYMBOL(flush_dcache_range) - -_GLOBAL(flush_inval_dcache_range) +_GLOBAL_TOC(flush_dcache_range) ld r10,PPC64_CACHES@toc(r2) lwz r7,DCACHEL1BLOCKSIZE(r10) /* Get dcache block size */ addi r5,r7,-1 @@ -164,7 +141,7 @@ _GLOBAL(flush_inval_dcache_range) sync isync blr - +EXPORT_SYMBOL(flush_dcache_range) /* * Flush a particular page from the data cache to RAM. |