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| author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2016-07-13 15:05:21 +0530 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-07-17 16:42:50 +1000 |
| commit | bf16cdf48a5369ba29614a0ade4ae5daf7a9e47c (patch) | |
| tree | 4abc3ff7bb6e15944e9a377bfe4a6064b457a402 /arch/powerpc/mm/pgtable-radix.c | |
| parent | 8cd6d3c23e226ec6cb8825e1aa6a391ebda71c72 (diff) | |
| download | linux-bf16cdf48a5369ba29614a0ade4ae5daf7a9e47c.tar.gz linux-bf16cdf48a5369ba29614a0ade4ae5daf7a9e47c.tar.bz2 linux-bf16cdf48a5369ba29614a0ade4ae5daf7a9e47c.zip | |
powerpc/mm/radix: Update LPCR HR bit as per ISA
PowerISA 3.0 requires the MMU mode (radix vs. hash) of the hypervisor
to be mirrored in the LPCR register, in addition to the partition table.
This is done to avoid fetching from the table when deciding, among other
things, how to perform transitions to HV mode on some interrupts.
So let's set it up appropriately
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Acked-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/mm/pgtable-radix.c')
| -rw-r--r-- | arch/powerpc/mm/pgtable-radix.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c index 7931e1496f0d..4732fa3fe591 100644 --- a/arch/powerpc/mm/pgtable-radix.c +++ b/arch/powerpc/mm/pgtable-radix.c @@ -342,7 +342,7 @@ void __init radix__early_init_mmu(void) radix_init_page_sizes(); if (!firmware_has_feature(FW_FEATURE_LPAR)) { lpcr = mfspr(SPRN_LPCR); - mtspr(SPRN_LPCR, lpcr | LPCR_UPRT); + mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); radix_init_partition_table(); } @@ -357,7 +357,7 @@ void radix__early_init_mmu_secondary(void) */ if (!firmware_has_feature(FW_FEATURE_LPAR)) { lpcr = mfspr(SPRN_LPCR); - mtspr(SPRN_LPCR, lpcr | LPCR_UPRT); + mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); |