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| author | Will Deacon <will.deacon@arm.com> | 2013-07-31 19:21:27 +0100 |
|---|---|---|
| committer | Joerg Roedel <joro@8bytes.org> | 2013-08-14 12:09:42 +0200 |
| commit | 1463fe44fd0f87af0404e2c147ab9724081b7235 (patch) | |
| tree | be7cfd49660f28164d41499348900f5987b81908 /arch/powerpc | |
| parent | adaba320916d246af56821a1aab81a715091e7e5 (diff) | |
| download | linux-1463fe44fd0f87af0404e2c147ab9724081b7235.tar.gz linux-1463fe44fd0f87af0404e2c147ab9724081b7235.tar.bz2 linux-1463fe44fd0f87af0404e2c147ab9724081b7235.zip | |
iommu/arm-smmu: Don't use VMIDs for stage-1 translations
Although permitted by the architecture, using VMIDs for stage-1
translations causes a complete nightmare for hypervisors, who end up
having to virtualise the VMID space across VMs, which may be using
multiple VMIDs each.
To make life easier for hypervisors (which might just decide not to
support this VMID virtualisation), this patch reworks the stage-1
context-bank TLB invalidation so that:
- Stage-1 mappings are marked non-global in the ptes
- Each Stage-1 context-bank is assigned an ASID in TTBR0
- VMID 0 is reserved for Stage-1 context-banks
This allows the hypervisor to overwrite the Stage-1 VMID in the CBAR
when trapping the write from the guest.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
Diffstat (limited to 'arch/powerpc')
0 files changed, 0 insertions, 0 deletions