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| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2024-02-22 16:39:45 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-03-12 07:13:18 -0700 |
| commit | 270fc77e7b0e38964635c2c5d87ad354dbd2cd34 (patch) | |
| tree | fdd27e3a77839121434201744cbef71c41210ff9 /arch/riscv/boot | |
| parent | 61609bf2b29dcb07de3aaad7d6212cc3c341192b (diff) | |
| download | linux-270fc77e7b0e38964635c2c5d87ad354dbd2cd34.tar.gz linux-270fc77e7b0e38964635c2c5d87ad354dbd2cd34.tar.bz2 linux-270fc77e7b0e38964635c2c5d87ad354dbd2cd34.zip | |
riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
xandespmu stands for Andes Performance Monitor Unit extension.
Based on the added Andes PMU ISA string, the SBI PMU driver
will make use of the non-standard irq source.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240222083946.3977135-10-peterlin@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/boot')
| -rw-r--r-- | arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index 099f3df75b42..d7a66043f13b 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -27,7 +27,7 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xandespmu"; mmu-type = "riscv,sv39"; i-cache-size = <0x8000>; i-cache-line-size = <0x40>; |