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| author | Kefeng Wang <wangkefeng.wang@huawei.com> | 2020-05-07 23:04:45 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-05-12 16:21:46 -0700 |
| commit | 48084c3595cb7429f6ba734cfea1313573b9a7fa (patch) | |
| tree | 305785d6b4ee85ea3d3c640e306a9cee466dc9bf /arch/riscv/include/asm/perf_event.h | |
| parent | e7b146a8bfba50e263745bbdefc11833c3766664 (diff) | |
| download | linux-48084c3595cb7429f6ba734cfea1313573b9a7fa.tar.gz linux-48084c3595cb7429f6ba734cfea1313573b9a7fa.tar.bz2 linux-48084c3595cb7429f6ba734cfea1313573b9a7fa.zip | |
riscv: perf: RISCV_BASE_PMU should be independent
Selecting PERF_EVENTS without selecting RISCV_BASE_PMU results in a build
error.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
[Palmer: commit text]
Fixes: 178e9fc47aae("perf: riscv: preliminary RISC-V support")
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/riscv/include/asm/perf_event.h')
| -rw-r--r-- | arch/riscv/include/asm/perf_event.h | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/riscv/include/asm/perf_event.h b/arch/riscv/include/asm/perf_event.h index 0234048b12bc..062efd3a1d5d 100644 --- a/arch/riscv/include/asm/perf_event.h +++ b/arch/riscv/include/asm/perf_event.h @@ -12,19 +12,14 @@ #include <linux/ptrace.h> #include <linux/interrupt.h> +#ifdef CONFIG_RISCV_BASE_PMU #define RISCV_BASE_COUNTERS 2 /* * The RISCV_MAX_COUNTERS parameter should be specified. */ -#ifdef CONFIG_RISCV_BASE_PMU #define RISCV_MAX_COUNTERS 2 -#endif - -#ifndef RISCV_MAX_COUNTERS -#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU." -#endif /* * These are the indexes of bits in counteren register *minus* 1, @@ -82,6 +77,7 @@ struct riscv_pmu { int irq; }; +#endif #ifdef CONFIG_PERF_EVENTS #define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs #endif |