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authorLinus Torvalds <torvalds@linux-foundation.org>2019-08-17 10:36:47 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2019-08-17 10:36:47 -0700
commit2f478b60118f48bf66eaddcca0d23e80f87a682d (patch)
tree9a4e6341f103e0e758f58b9db3e3d3a325145737 /arch/riscv/include/asm/pgtable-64.h
parent6e625a1a3f471d63989d3a66cdf6a0c307654848 (diff)
parent69703eb9a8ae28a46cd5bce7d69ceeef6273a104 (diff)
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Merge tag 'riscv/for-v5.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Paul Walmsley: - Two patches to fix significant bugs in floating point register context handling - A minor fix in RISC-V flush_tlb_page(), to supply a valid end address to flush_tlb_range() - Two minor defconfig additions: to build the virtio hwrng driver by default (for QEMU targets), and to partially synchronize the 32-bit defconfig with the 64-bit defconfig * tag 'riscv/for-v5.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Make __fstate_clean() work correctly. riscv: Correct the initialized flow of FP register riscv: defconfig: Update the defconfig riscv: rv32_defconfig: Update the defconfig riscv: fix flush_tlb_range() end address for flush_tlb_page()
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