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| author | Christoph Hellwig <hch@lst.de> | 2019-08-21 23:58:37 +0900 |
|---|---|---|
| committer | Paul Walmsley <paul.walmsley@sifive.com> | 2019-09-05 01:54:51 -0700 |
| commit | 95594cb40c6e013e04659f7316fbdebe83913c58 (patch) | |
| tree | c76bb919d36e75cd7e1fb77d585665284694dca4 /arch/riscv/mm/Makefile | |
| parent | 2f12dbf190d97dc0f2f8a07269dd0d8060808539 (diff) | |
| download | linux-95594cb40c6e013e04659f7316fbdebe83913c58.tar.gz linux-95594cb40c6e013e04659f7316fbdebe83913c58.tar.bz2 linux-95594cb40c6e013e04659f7316fbdebe83913c58.zip | |
riscv: move the TLB flush logic out of line
The TLB flush logic is going to become more complex. Start moving
it out of line.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
[paul.walmsley@sifive.com: fixed checkpatch whitespace warnings]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch/riscv/mm/Makefile')
| -rw-r--r-- | arch/riscv/mm/Makefile | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index 74055e1d6f21..9d9a17335686 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -13,4 +13,7 @@ obj-y += cacheflush.o obj-y += context.o obj-y += sifive_l2_cache.o +ifeq ($(CONFIG_MMU),y) +obj-$(CONFIG_SMP) += tlbflush.o +endif obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o |