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author | Mark Brown <broonie@kernel.org> | 2023-04-11 16:11:32 +0100 |
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committer | Mark Brown <broonie@kernel.org> | 2023-04-11 16:11:32 +0100 |
commit | 53e59b5c4645236f0014d3cc5c24bc71ad3f6120 (patch) | |
tree | 64c6005d6ffd496454fffb05b584ffb7011e12b4 /arch/riscv/mm/context.c | |
parent | 60bbee7db43b97bf8c0978cc91f78d1746351871 (diff) | |
parent | a27e71a66ee0f887fefcc31b85a804b0905fa865 (diff) | |
download | linux-53e59b5c4645236f0014d3cc5c24bc71ad3f6120.tar.gz linux-53e59b5c4645236f0014d3cc5c24bc71ad3f6120.tar.bz2 linux-53e59b5c4645236f0014d3cc5c24bc71ad3f6120.zip |
Add support for Rockchip RK860X regulators
Merge series from Cristian Ciocaltea <cristian.ciocaltea@collabora.com>:
This patch series introduces support for the Rockchip RK860X regulators,
while also providing a few fixes and improvements to the existing fan53555
driver.
RK8600/RK8601 are quite similar to the FAN53555 regulators.
RK8602/RK8603 are a bit different, having a wider output voltage
selection range, from 0.5 V to 1.5 V in 6.25 mV steps. They are used
in the Rock 5B board to power the ARM Cortex-A76 cores and the NPU.
Diffstat (limited to 'arch/riscv/mm/context.c')
-rw-r--r-- | arch/riscv/mm/context.c | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 80ce9caba8d2..12e22e7330e7 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -22,7 +22,7 @@ DEFINE_STATIC_KEY_FALSE(use_asid_allocator); static unsigned long asid_bits; static unsigned long num_asids; -static unsigned long asid_mask; +unsigned long asid_mask; static atomic_long_t current_version; @@ -196,16 +196,6 @@ switch_mm_fast: if (need_flush_tlb) local_flush_tlb_all(); -#ifdef CONFIG_SMP - else { - cpumask_t *mask = &mm->context.tlb_stale_mask; - - if (cpumask_test_cpu(cpu, mask)) { - cpumask_clear_cpu(cpu, mask); - local_flush_tlb_all_asid(cntx & asid_mask); - } - } -#endif } static void set_mm_noasid(struct mm_struct *mm) @@ -215,12 +205,24 @@ static void set_mm_noasid(struct mm_struct *mm) local_flush_tlb_all(); } -static inline void set_mm(struct mm_struct *mm, unsigned int cpu) +static inline void set_mm(struct mm_struct *prev, + struct mm_struct *next, unsigned int cpu) { - if (static_branch_unlikely(&use_asid_allocator)) - set_mm_asid(mm, cpu); - else - set_mm_noasid(mm); + /* + * The mm_cpumask indicates which harts' TLBs contain the virtual + * address mapping of the mm. Compared to noasid, using asid + * can't guarantee that stale TLB entries are invalidated because + * the asid mechanism wouldn't flush TLB for every switch_mm for + * performance. So when using asid, keep all CPUs footmarks in + * cpumask() until mm reset. + */ + cpumask_set_cpu(cpu, mm_cpumask(next)); + if (static_branch_unlikely(&use_asid_allocator)) { + set_mm_asid(next, cpu); + } else { + cpumask_clear_cpu(cpu, mm_cpumask(prev)); + set_mm_noasid(next); + } } static int __init asids_init(void) @@ -274,7 +276,8 @@ static int __init asids_init(void) } early_initcall(asids_init); #else -static inline void set_mm(struct mm_struct *mm, unsigned int cpu) +static inline void set_mm(struct mm_struct *prev, + struct mm_struct *next, unsigned int cpu) { /* Nothing to do here when there is no MMU */ } @@ -327,10 +330,7 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next, */ cpu = smp_processor_id(); - cpumask_clear_cpu(cpu, mm_cpumask(prev)); - cpumask_set_cpu(cpu, mm_cpumask(next)); - - set_mm(next, cpu); + set_mm(prev, next, cpu); flush_icache_deferred(next, cpu); } |