diff options
| author | Conor Dooley <conor.dooley@microchip.com> | 2022-08-10 09:59:15 +0100 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2022-08-15 21:07:41 +0100 |
| commit | 7eac0081a8e958106ed3aea402c8105f30fad6d9 (patch) | |
| tree | 3c3f672a16c6357efee8c61e0e50005d3ae2a0e4 /arch/riscv | |
| parent | 69dac8e431af26173ca0a1ebc87054e01c585bcc (diff) | |
| download | linux-7eac0081a8e958106ed3aea402c8105f30fad6d9.tar.gz linux-7eac0081a8e958106ed3aea402c8105f30fad6d9.tar.bz2 linux-7eac0081a8e958106ed3aea402c8105f30fad6d9.zip | |
riscv: dts: microchip: add qspi compatible fallback
The "hard" QSPI peripheral on PolarFire SoC is derived from version 2
of the FPGA IP core. The original binding had no fallback etc, so this
device tree is valid as is. There was also no functional driver for the
QSPI IP, so no device with a devicetree from a previous mainline
release will regress.
Link: https://lore.kernel.org/linux-spi/7c9f0d96-2882-964a-cd1f-916ddb3f0410@linaro.org/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 499c2e63ad35..45e3cc659882 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -330,7 +330,7 @@ }; qspi: spi@21000000 { - compatible = "microchip,mpfs-qspi"; + compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x21000000 0x0 0x1000>; |