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| author | Anup Patel <apatel@ventanamicro.com> | 2022-04-09 09:15:33 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-04-09 09:15:33 +0530 |
| commit | 8c3ce496bd612bd21679e445f75fcabb6be997b2 (patch) | |
| tree | f8d6345007c66c77ce957a29a73bdff6a975a15f /arch/riscv | |
| parent | a44e2c207c30a5780c4ad0cc3579b8715cebf52e (diff) | |
| download | linux-8c3ce496bd612bd21679e445f75fcabb6be997b2.tar.gz linux-8c3ce496bd612bd21679e445f75fcabb6be997b2.tar.bz2 linux-8c3ce496bd612bd21679e445f75fcabb6be997b2.zip | |
RISC-V: KVM: Don't clear hgatp CSR in kvm_arch_vcpu_put()
We might have RISC-V systems (such as QEMU) where VMID is not part
of the TLB entry tag so these systems will have to flush all TLB
entries upon any change in hgatp.VMID.
Currently, we zero-out hgatp CSR in kvm_arch_vcpu_put() and we
re-program hgatp CSR in kvm_arch_vcpu_load(). For above described
systems, this will flush all TLB entries whenever VCPU exits to
user-space hence reducing performance.
This patch fixes above described performance issue by not clearing
hgatp CSR in kvm_arch_vcpu_put().
Fixes: 34bde9d8b9e6 ("RISC-V: KVM: Implement VCPU world-switch")
Cc: stable@vger.kernel.org
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/kvm/vcpu.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 624166004e36..6785aef4cbd4 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -653,8 +653,6 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) vcpu->arch.isa); kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); - csr_write(CSR_HGATP, 0); - csr->vsstatus = csr_read(CSR_VSSTATUS); csr->vsie = csr_read(CSR_VSIE); csr->vstvec = csr_read(CSR_VSTVEC); |