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authorChristoph Hellwig <hch@lst.de>2018-08-04 10:23:15 +0200
committerPalmer Dabbelt <palmer@sifive.com>2018-08-13 08:31:31 -0700
commitbec2e6ac353d5c8a47c6eea639136bac3990093e (patch)
tree3d3b751c630c5a550c86b7d6633d6c2d747a8c7a /arch/riscv
parent4b40e9ddc892de508c3b3a3d82ee568c07c4308a (diff)
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RISC-V: add a definition for the SIE SEIE bit
This mirrors the SIE_SSIE and SETE bits that are used in a similar fashion. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/include/asm/csr.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 421fa3585798..28a0d1cb374c 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -54,6 +54,7 @@
/* Interrupt Enable and Interrupt Pending flags */
#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */
#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */
+#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */
#define EXC_INST_MISALIGNED 0
#define EXC_INST_ACCESS 1