diff options
| author | Kan Liang <kan.liang@linux.intel.com> | 2020-09-28 05:30:41 -0700 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2020-09-29 09:57:01 +0200 |
| commit | dbfd638889a0396f5fe14ff3cc2263ec1e1cac62 (patch) | |
| tree | 648426961e9ce66e1d238a69f506ca517cd42fc7 /arch/x86/events | |
| parent | ee139385432e919f4d1f59b80edbc073cdae1391 (diff) | |
| download | linux-dbfd638889a0396f5fe14ff3cc2263ec1e1cac62.tar.gz linux-dbfd638889a0396f5fe14ff3cc2263ec1e1cac62.tar.bz2 linux-dbfd638889a0396f5fe14ff3cc2263ec1e1cac62.zip | |
perf/x86/intel: Add Jasper Lake support
The Jasper Lake processor is also a Tremont microarchitecture. From the
perspective of Intel PMU, there is nothing changed compared with
Elkhart Lake.
Share the perf code with Elkhart Lake.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1601296242-32763-1-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events')
| -rw-r--r-- | arch/x86/events/intel/core.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index c72e4904e056..75dea6746d2d 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5135,6 +5135,7 @@ __init int intel_pmu_init(void) case INTEL_FAM6_ATOM_TREMONT_D: case INTEL_FAM6_ATOM_TREMONT: + case INTEL_FAM6_ATOM_TREMONT_L: x86_pmu.late_ack = true; memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); |