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| author | Yazen Ghannam <yazen.ghannam@amd.com> | 2024-06-06 11:12:57 -0500 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2024-06-12 11:38:58 +0200 |
| commit | dc5243921be1b6a0b4259dbcec3dc95016ad8427 (patch) | |
| tree | 7720b7401dece7f39bd57f5e3f76229bb5c0f838 /arch/x86/include/asm/amd_nb.h | |
| parent | c2d79cc5455c891de6c93e1e0c73d806e299c54f (diff) | |
| download | linux-dc5243921be1b6a0b4259dbcec3dc95016ad8427.tar.gz linux-dc5243921be1b6a0b4259dbcec3dc95016ad8427.tar.bz2 linux-dc5243921be1b6a0b4259dbcec3dc95016ad8427.zip | |
x86/amd_nb: Enhance SMN access error checking
AMD Zen-based systems use a System Management Network (SMN) that
provides access to implementation-specific registers.
SMN accesses are done indirectly through an index/data pair in PCI
config space. The accesses can fail for a variety of reasons.
Include code comments to describe some possible scenarios.
Require error checking for callers of amd_smn_read() and amd_smn_write().
This is needed because many error conditions cannot be checked by these
functions.
[ bp: Touchup comment. ]
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20240606-fix-smn-bad-read-v4-4-ffde21931c3f@amd.com
Diffstat (limited to 'arch/x86/include/asm/amd_nb.h')
| -rw-r--r-- | arch/x86/include/asm/amd_nb.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 5c37944c8a5e..6f3b6aef47ba 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -21,8 +21,8 @@ extern int amd_numa_init(void); extern int amd_get_subcaches(int); extern int amd_set_subcaches(int, unsigned long); -extern int amd_smn_read(u16 node, u32 address, u32 *value); -extern int amd_smn_write(u16 node, u32 address, u32 value); +int __must_check amd_smn_read(u16 node, u32 address, u32 *value); +int __must_check amd_smn_write(u16 node, u32 address, u32 value); struct amd_l3_cache { unsigned indices; |