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| author | Thomas Gleixner <tglx@linutronix.de> | 2020-10-27 11:09:50 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2020-11-11 14:35:16 +0100 |
| commit | 5f0c71278d6848b4809f83af90f28196e1505ab1 (patch) | |
| tree | 0478702fab51eaf11f32cde8e77dccebf857a53c /arch/x86/include | |
| parent | f8394f232b1eab649ce2df5c5f15b0e528c92091 (diff) | |
| download | linux-5f0c71278d6848b4809f83af90f28196e1505ab1.tar.gz linux-5f0c71278d6848b4809f83af90f28196e1505ab1.tar.bz2 linux-5f0c71278d6848b4809f83af90f28196e1505ab1.zip | |
x86/fpu: Simplify fpregs_[un]lock()
There is no point in disabling preemption and then disabling bottom
halfs.
Just disabling bottom halfs is sufficient as it implicitly disables
preemption on !RT kernels.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20201027101349.455380473@linutronix.de
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/fpu/api.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/x86/include/asm/fpu/api.h b/arch/x86/include/asm/fpu/api.h index dcd9503b1098..2c5bef78a484 100644 --- a/arch/x86/include/asm/fpu/api.h +++ b/arch/x86/include/asm/fpu/api.h @@ -29,17 +29,18 @@ extern void fpregs_mark_activate(void); * A context switch will (and softirq might) save CPU's FPU registers to * fpu->state and set TIF_NEED_FPU_LOAD leaving CPU's FPU registers in * a random state. + * + * local_bh_disable() protects against both preemption and soft interrupts + * on !RT kernels. */ static inline void fpregs_lock(void) { - preempt_disable(); local_bh_disable(); } static inline void fpregs_unlock(void) { local_bh_enable(); - preempt_enable(); } #ifdef CONFIG_X86_DEBUG_FPU |