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| author | Thomas Gleixner <tglx@linutronix.de> | 2023-08-14 10:18:45 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2023-10-10 14:38:19 +0200 |
| commit | db4a4086a223bd5cbfa5a66701c493124d808d55 (patch) | |
| tree | b4f64fee63f3e96ee397211d32a796e60cd5157a /arch/x86/kernel/apic/x2apic_uv_x.c | |
| parent | 59f7928cd46316371bee71b0cb34e133567e5b35 (diff) | |
| download | linux-db4a4086a223bd5cbfa5a66701c493124d808d55.tar.gz linux-db4a4086a223bd5cbfa5a66701c493124d808d55.tar.bz2 linux-db4a4086a223bd5cbfa5a66701c493124d808d55.zip | |
x86/apic: Use u32 for wakeup_secondary_cpu[_64]()
APIC IDs are used with random data types u16, u32, int, unsigned int,
unsigned long.
Make it all consistently use u32 because that reflects the hardware
register width.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Tested-by: Sohil Mehta <sohil.mehta@intel.com>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20230814085113.233274223@linutronix.de
Diffstat (limited to 'arch/x86/kernel/apic/x2apic_uv_x.c')
| -rw-r--r-- | arch/x86/kernel/apic/x2apic_uv_x.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index 46d4de2f00a1..6efc499d5c14 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -701,7 +701,7 @@ static __init void build_uv_gr_table(void) } } -static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) +static int uv_wakeup_secondary(u32 phys_apicid, unsigned long start_rip) { unsigned long val; int pnode; |