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| author | Pawan Gupta <pawan.kumar.gupta@linux.intel.com> | 2021-06-14 14:14:25 -0700 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2021-06-15 17:46:48 +0200 |
| commit | 293649307ef9abcd4f83f6dac4d4400dfd97c936 (patch) | |
| tree | 745286c3c1d2ef6bc847a92046bb619bb47d02f0 /arch/x86/kernel/cpu/intel.c | |
| parent | ad3c2e174938d72fded674acead42e2464a3b460 (diff) | |
| download | linux-293649307ef9abcd4f83f6dac4d4400dfd97c936.tar.gz linux-293649307ef9abcd4f83f6dac4d4400dfd97c936.tar.bz2 linux-293649307ef9abcd4f83f6dac4d4400dfd97c936.zip | |
x86/tsx: Clear CPUID bits when TSX always force aborts
As a result of TSX deprecation, some processors always abort TSX
transactions by default after a microcode update.
When TSX feature cannot be used it is better to hide it. Clear CPUID.RTM
and CPUID.HLE bits when TSX transactions always abort.
[ bp: Massage commit message and comments. ]
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Tested-by: Neelima Krishnan <neelima.krishnan@intel.com>
Link: https://lkml.kernel.org/r/5209b3d72ffe5bd3cafdcc803f5b883f785329c3.1623704845.git-series.pawan.kumar.gupta@linux.intel.com
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 8adffc17fa8b..861e919eba9a 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -717,8 +717,10 @@ static void init_intel(struct cpuinfo_x86 *c) if (tsx_ctrl_state == TSX_CTRL_ENABLE) tsx_enable(); - if (tsx_ctrl_state == TSX_CTRL_DISABLE) + else if (tsx_ctrl_state == TSX_CTRL_DISABLE) tsx_disable(); + else if (tsx_ctrl_state == TSX_CTRL_RTM_ALWAYS_ABORT) + tsx_clear_cpuid(); split_lock_init(); bus_lock_init(); |