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authorLinus Torvalds <torvalds@linux-foundation.org>2016-07-26 10:26:29 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2016-07-26 10:26:29 -0700
commit37e13a1ebe32c4fbfbdb5413f42eb6e71d8b28a4 (patch)
tree1921a0702d41d655d4b9a2115bc9bbff5f0b2d6b /arch/x86/lib/insn.c
parente65805251f2db69c9f67ed8062ab82526be5a374 (diff)
parent674d2d69b14f677a771ceec4b48bfade94a0c5f1 (diff)
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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Ingo Molnar: "This tree contains tooling fixes plus some additions: - fixes to the vdso2c build environment that Stephen Rothwell is using for the linux-next build (Arnaldo Carvalho de Melo) - AVX-512 instruction mappings (Adrian Hunter) - misc fixes" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: Revert "perf tools: event.h needs asm/perf_regs.h" x86: Make the vdso2c compiler use the host architecture headers tools build: Fix objtool build with ARCH=x86_64 objtool: Always use host headers objtool: Use tools/scripts/Makefile.arch to get ARCH and HOSTARCH tools build: Add HOSTARCH Makefile variable perf tests kmod-path: Fix build on ubuntu:16.04-x-armhf perf tools: Add AVX-512 instructions to the new instructions test perf tools: Add AVX-512 support to the instruction decoder used by Intel PT x86/insn: Add AVX-512 support to the instruction decoder x86/insn: perf tools: Fix vcvtph2ps instruction decoding
Diffstat (limited to 'arch/x86/lib/insn.c')
-rw-r--r--arch/x86/lib/insn.c18
1 files changed, 15 insertions, 3 deletions
diff --git a/arch/x86/lib/insn.c b/arch/x86/lib/insn.c
index 1a416935bac9..1088eb8f3a5f 100644
--- a/arch/x86/lib/insn.c
+++ b/arch/x86/lib/insn.c
@@ -155,14 +155,24 @@ found:
/*
* In 32-bits mode, if the [7:6] bits (mod bits of
* ModRM) on the second byte are not 11b, it is
- * LDS or LES.
+ * LDS or LES or BOUND.
*/
if (X86_MODRM_MOD(b2) != 3)
goto vex_end;
}
insn->vex_prefix.bytes[0] = b;
insn->vex_prefix.bytes[1] = b2;
- if (inat_is_vex3_prefix(attr)) {
+ if (inat_is_evex_prefix(attr)) {
+ b2 = peek_nbyte_next(insn_byte_t, insn, 2);
+ insn->vex_prefix.bytes[2] = b2;
+ b2 = peek_nbyte_next(insn_byte_t, insn, 3);
+ insn->vex_prefix.bytes[3] = b2;
+ insn->vex_prefix.nbytes = 4;
+ insn->next_byte += 4;
+ if (insn->x86_64 && X86_VEX_W(b2))
+ /* VEX.W overrides opnd_size */
+ insn->opnd_bytes = 8;
+ } else if (inat_is_vex3_prefix(attr)) {
b2 = peek_nbyte_next(insn_byte_t, insn, 2);
insn->vex_prefix.bytes[2] = b2;
insn->vex_prefix.nbytes = 3;
@@ -221,7 +231,9 @@ void insn_get_opcode(struct insn *insn)
m = insn_vex_m_bits(insn);
p = insn_vex_p_bits(insn);
insn->attr = inat_get_avx_attribute(op, m, p);
- if (!inat_accept_vex(insn->attr) && !inat_is_group(insn->attr))
+ if ((inat_must_evex(insn->attr) && !insn_is_evex(insn)) ||
+ (!inat_accept_vex(insn->attr) &&
+ !inat_is_group(insn->attr)))
insn->attr = 0; /* This instruction is bad */
goto end; /* VEX has only 1 byte for opcode */
}