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| author | Mukesh Rathor <mukesh.rathor@oracle.com> | 2014-09-10 16:36:06 -0700 |
|---|---|---|
| committer | David Vrabel <david.vrabel@citrix.com> | 2014-10-06 10:27:47 +0100 |
| commit | a2ef5dc2c7cbedbeb4c847039845afaea5e63745 (patch) | |
| tree | 0dc9014daac67ace499d36cd1051cda7acc68271 /arch/x86/xen/xen-head.S | |
| parent | d1e9abd630fe66046087f6501a4e4b8de55f7ab9 (diff) | |
| download | linux-a2ef5dc2c7cbedbeb4c847039845afaea5e63745.tar.gz linux-a2ef5dc2c7cbedbeb4c847039845afaea5e63745.tar.bz2 linux-a2ef5dc2c7cbedbeb4c847039845afaea5e63745.zip | |
x86/xen: Set EFER.NX and EFER.SCE in PVH guests
This fixes two bugs in PVH guests:
- Not setting EFER.NX means the NX bit in page table entries is
ignored on Intel processors and causes reserved bit page faults on
AMD processors.
- After the Xen commit 7645640d6ff1 ("x86/PVH: don't set EFER_SCE for
pvh guest") PVH guests are required to set EFER.SCE to enable the
SYSCALL instruction.
Secondary VCPUs are started with pagetables with the NX bit set so
EFER.NX must be set before using any stack or data segment.
xen_pvh_cpu_early_init() is the new secondary VCPU entry point that
sets EFER before jumping to cpu_bringup_and_idle().
Signed-off-by: Mukesh Rathor <mukesh.rathor@oracle.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: David Vrabel <david.vrabel@citrix.com>
Diffstat (limited to 'arch/x86/xen/xen-head.S')
| -rw-r--r-- | arch/x86/xen/xen-head.S | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S index 46408e51c1dc..674b222544b7 100644 --- a/arch/x86/xen/xen-head.S +++ b/arch/x86/xen/xen-head.S @@ -47,6 +47,41 @@ ENTRY(startup_xen) __FINIT +#ifdef CONFIG_XEN_PVH +/* + * xen_pvh_early_cpu_init() - early PVH VCPU initialization + * @cpu: this cpu number (%rdi) + * @entry: true if this is a secondary vcpu coming up on this entry + * point, false if this is the boot CPU being initialized for + * the first time (%rsi) + * + * Note: This is called as a function on the boot CPU, and is the entry point + * on the secondary CPU. + */ +ENTRY(xen_pvh_early_cpu_init) + mov %rsi, %r11 + + /* Gather features to see if NX implemented. */ + mov $0x80000001, %eax + cpuid + mov %edx, %esi + + mov $MSR_EFER, %ecx + rdmsr + bts $_EFER_SCE, %eax + + bt $20, %esi + jnc 1f /* No NX, skip setting it */ + bts $_EFER_NX, %eax +1: wrmsr +#ifdef CONFIG_SMP + cmp $0, %r11b + jne cpu_bringup_and_idle +#endif + ret + +#endif /* CONFIG_XEN_PVH */ + .pushsection .text .balign PAGE_SIZE ENTRY(hypercall_page) |