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authorAndrea Venturi <ennesimamail.av@gmail.com>2016-03-21 17:10:38 +0100
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-04-22 00:29:21 +0200
commit8f0767611a0ed719caf975d899d8431834ace2d8 (patch)
tree5c5bf867e6b491b5c2e408ab8c9191461e96c68c /arch
parent92a39d9043ba5ff98adb1c31491f00c7bea5466e (diff)
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clk: sunxi: mod1 clock should modify it's parent
add CLK_SET_RATE_PARENT to modify the rate on clk upstream Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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