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authorPaul Burton <paul.burton@imgtec.com>2017-06-02 15:38:03 -0700
committerRalf Baechle <ralf@linux-mips.org>2017-06-29 02:42:29 +0200
commitcebf8c0f4f4e378f5e82606023b92ffbb1ad6048 (patch)
tree0fbb2a5b8638b0d288e20c18e821ecc93ed103d3 /arch
parentf39878cc5b09c75d35eaf52131e920b872e3feb4 (diff)
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MIPS: Allow storing pgd in C0_CONTEXT for MIPSr6
CONFIG_MIPS_PGD_C0_CONTEXT, which allows a pointer to the page directory to be stored in the cop0 Context register when enabled, was previously only allowed for MIPSr2. MIPSr6 is just as able to make use of it, so allow it there too. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16204/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a986116dabb5..609986e8b21e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2073,7 +2073,7 @@ config CPU_SUPPORTS_UNCACHED_ACCELERATED
bool
config MIPS_PGD_C0_CONTEXT
bool
- default y if 64BIT && CPU_MIPSR2 && !CPU_XLP
+ default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
#
# Set to y for ptrace access to watch registers.