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| author | Rocky Hao <rocky.hao@rock-chips.com> | 2017-08-24 18:27:53 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-10-17 20:53:29 +0200 |
| commit | fb03abbc2755a7f0efb245b926c0f5ba39683da6 (patch) | |
| tree | f50e498ccdd85f37dc592340c298ff194086e0a5 /arch | |
| parent | faf15c0b750f3df74509345e1c37a29d1705f8af (diff) | |
| download | linux-fb03abbc2755a7f0efb245b926c0f5ba39683da6.tar.gz linux-fb03abbc2755a7f0efb245b926c0f5ba39683da6.tar.bz2 linux-fb03abbc2755a7f0efb245b926c0f5ba39683da6.zip | |
ARM: dts: rockchip: add tsadc node for RV1108 SoC
Add tsadc needed main information for RV1108 SoC.
750000Hz is the max clock rate supported by tsadc module.
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/rv1108.dtsi | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index e7cd1315db1b..658a458a5b38 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -329,6 +329,25 @@ status = "disabled"; }; + tsadc: tsadc@10370000 { + compatible = "rockchip,rv1108-tsadc"; + reg = <0x10370000 0x100>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <750000>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + rockchip,hw-tshut-temp = <120000>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + adc: adc@1038c000 { compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; reg = <0x1038c000 0x100>; @@ -740,6 +759,16 @@ }; }; + tsadc { + otp_out: otp-out { + rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; + }; + + otp_gpio: otp-gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, |