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author | Arnd Bergmann <arnd@arndb.de> | 2013-06-20 21:37:55 +0200 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2013-06-20 21:37:55 +0200 |
commit | b31a76546c08f618e355bd12a7cc138c045374b7 (patch) | |
tree | bc1aba4774e8f4910253c1eb409de278178dfed5 /drivers/acpi/apei/cper.c | |
parent | 4a77a932b9958ffd393581cd5350ca0ef39711de (diff) | |
parent | 45853507c9362b0bd606b37e8c7c7e7551caa78b (diff) | |
download | linux-b31a76546c08f618e355bd12a7cc138c045374b7.tar.gz linux-b31a76546c08f618e355bd12a7cc138c045374b7.tar.bz2 linux-b31a76546c08f618e355bd12a7cc138c045374b7.zip |
Merge tag 'omap-for-v3.11/board-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/boards
From Tony Lindgren:
Minor board changes for v3.11 merge window. These are
tapering down finally as we're getting closer to making
omap2+ DT only.
* tag 'omap-for-v3.11/board-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: omap2plus_defconfig: enable USB_PHY and NOP_USB_XCEIV
ARM: OMAP1: nokia770: enable Tahvo
ARM: OMAP3EVM: Marking omap3_evm_display_init() with CONFIG_BROKEN
arm: omap: board-overo: reset GPIO for SMSC911x
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/acpi/apei/cper.c')
-rw-r--r-- | drivers/acpi/apei/cper.c | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/drivers/acpi/apei/cper.c b/drivers/acpi/apei/cper.c index fefc2ca7cc3e..33dc6a004802 100644 --- a/drivers/acpi/apei/cper.c +++ b/drivers/acpi/apei/cper.c @@ -250,10 +250,6 @@ static const char *cper_pcie_port_type_strs[] = { static void cper_print_pcie(const char *pfx, const struct cper_sec_pcie *pcie, const struct acpi_hest_generic_data *gdata) { -#ifdef CONFIG_ACPI_APEI_PCIEAER - struct pci_dev *dev; -#endif - if (pcie->validation_bits & CPER_PCIE_VALID_PORT_TYPE) printk("%s""port_type: %d, %s\n", pfx, pcie->port_type, pcie->port_type < ARRAY_SIZE(cper_pcie_port_type_strs) ? @@ -285,20 +281,6 @@ static void cper_print_pcie(const char *pfx, const struct cper_sec_pcie *pcie, printk( "%s""bridge: secondary_status: 0x%04x, control: 0x%04x\n", pfx, pcie->bridge.secondary_status, pcie->bridge.control); -#ifdef CONFIG_ACPI_APEI_PCIEAER - dev = pci_get_domain_bus_and_slot(pcie->device_id.segment, - pcie->device_id.bus, pcie->device_id.function); - if (!dev) { - pr_err("PCI AER Cannot get PCI device %04x:%02x:%02x.%d\n", - pcie->device_id.segment, pcie->device_id.bus, - pcie->device_id.slot, pcie->device_id.function); - return; - } - if (pcie->validation_bits & CPER_PCIE_VALID_AER_INFO) - cper_print_aer(pfx, dev, gdata->error_severity, - (struct aer_capability_regs *) pcie->aer_info); - pci_dev_put(dev); -#endif } static const char *apei_estatus_section_flag_strs[] = { |