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| author | Hannes Reinecke <hare@suse.de> | 2021-12-21 08:21:25 +0100 |
|---|---|---|
| committer | Damien Le Moal <damien.lemoal@opensource.wdc.com> | 2022-01-05 19:33:03 +0900 |
| commit | cb8d5daae9adcc5dac44c068d5d795056aa6d30c (patch) | |
| tree | 97aecd80e4c8bca31c8e0cdb89e2012e9433591b /drivers/ata | |
| parent | cb3f48fc57508aea8698e0bee99068fddde30ad9 (diff) | |
| download | linux-cb8d5daae9adcc5dac44c068d5d795056aa6d30c.tar.gz linux-cb8d5daae9adcc5dac44c068d5d795056aa6d30c.tar.bz2 linux-cb8d5daae9adcc5dac44c068d5d795056aa6d30c.zip | |
ata: pata_hpt3x2n: convert pr_XXX() calls
Convert pr_XXX() calls to structured logging.
Signed-off-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Diffstat (limited to 'drivers/ata')
| -rw-r--r-- | drivers/ata/pata_hpt3x2n.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/drivers/ata/pata_hpt3x2n.c b/drivers/ata/pata_hpt3x2n.c index 48eef338e050..1d9d4eec5b8a 100644 --- a/drivers/ata/pata_hpt3x2n.c +++ b/drivers/ata/pata_hpt3x2n.c @@ -15,9 +15,6 @@ * TODO * Work out best PLL policy */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> @@ -420,7 +417,7 @@ static int hpt3x2n_pci_clock(struct pci_dev *pdev) u16 sr; u32 total = 0; - pr_warn("BIOS clock data not set\n"); + dev_warn(&pdev->dev, "BIOS clock data not set\n"); /* This is the process the HPT371 BIOS is reported to use */ for (i = 0; i < 128; i++) { @@ -530,7 +527,8 @@ hpt372n: ppi[0] = &info_hpt372n; break; default: - pr_err("PCI table is bogus, please report (%d)\n", dev->device); + dev_err(&dev->dev,"PCI table is bogus, please report (%d)\n", + dev->device); return -ENODEV; } @@ -579,11 +577,11 @@ hpt372n: pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); } if (adjust == 8) { - pr_err("DPLL did not stabilize!\n"); + dev_err(&dev->dev, "DPLL did not stabilize!\n"); return -ENODEV; } - pr_info("bus clock %dMHz, using 66MHz DPLL\n", pci_mhz); + dev_info(&dev->dev, "bus clock %dMHz, using 66MHz DPLL\n", pci_mhz); /* * Set our private data up. We only need a few flags |