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| author | Boris BREZILLON <b.brezillon@overkiz.com> | 2013-10-11 10:48:26 +0200 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2013-12-02 15:31:22 +0100 |
| commit | 1a748d2bc5061b72588013a720645661345c0e65 (patch) | |
| tree | e27047e6a1437f2cdc3a737d0472f629d0e9f7ca /drivers/clk/at91/pmc.h | |
| parent | 38d34c3120b5588e2bd561baa4c5cfef1a4917bb (diff) | |
| download | linux-1a748d2bc5061b72588013a720645661345c0e65.tar.gz linux-1a748d2bc5061b72588013a720645661345c0e65.tar.bz2 linux-1a748d2bc5061b72588013a720645661345c0e65.zip | |
clk: at91: add PMC pll clocks
This patch adds new at91 pll clock implementation using common clk framework.
The pll clock layout describe the PLLX register layout.
There are four pll clock layouts:
- at91rm9200
- at91sam9g20
- at91sam9g45
- sama5d3
PLL clocks are given characteristics:
- min/max clock source rate
- ranges of valid clock output rates
- values to set in out and icpll fields for each supported output range
These characteristics are checked during rate change to avoid
over/underclocking.
These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'drivers/clk/at91/pmc.h')
| -rw-r--r-- | drivers/clk/at91/pmc.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 729aa46c7289..15aaf38e37c5 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -61,4 +61,15 @@ int of_at91_get_clk_range(struct device_node *np, const char *propname, extern void __init of_at91rm9200_clk_main_setup(struct device_node *np, struct at91_pmc *pmc); +extern void __init of_at91rm9200_clk_pll_setup(struct device_node *np, + struct at91_pmc *pmc); +extern void __init of_at91sam9g45_clk_pll_setup(struct device_node *np, + struct at91_pmc *pmc); +extern void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np, + struct at91_pmc *pmc); +extern void __init of_sama5d3_clk_pll_setup(struct device_node *np, + struct at91_pmc *pmc); +extern void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np, + struct at91_pmc *pmc); + #endif /* __PMC_H_ */ |