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author | Abel Vesa <abel.vesa@nxp.com> | 2019-02-22 17:07:32 +0000 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2019-02-26 10:09:31 -0800 |
commit | e9dda4af685ff4c19cd9236e12c1ee0377696843 (patch) | |
tree | 282ba0ef5e7bd86527b4f59245c66ec28fd61bca /drivers/clk/imx/clk.h | |
parent | 3b9ea606cda533964985966ad5b30715da7ba097 (diff) | |
download | linux-e9dda4af685ff4c19cd9236e12c1ee0377696843.tar.gz linux-e9dda4af685ff4c19cd9236e12c1ee0377696843.tar.bz2 linux-e9dda4af685ff4c19cd9236e12c1ee0377696843.zip |
clk: imx: Refactor entire sccg pll clk
Make the entire combination of plls to be one single clock. The parents used
for bypasses are specified each as an index in the parents list.
The determine_rate does a lookup throughout all the possible combinations
for all the divs and returns the best possible 'setup' which in turn is used
by set_rate later to set up all the divs and bypasses.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Tested-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/imx/clk.h')
-rw-r--r-- | drivers/clk/imx/clk.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 0aa48d3e3b95..5748ec8673e4 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -60,9 +60,12 @@ struct clk *imx_clk_pllv2(const char *name, const char *parent, struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, void __iomem *base); -struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name, - void __iomem *base, - enum imx_sccg_pll_type pll_type); +struct clk *imx_clk_sccg_pll(const char *name, + const char * const *parent_names, + u8 num_parents, + u8 parent, u8 bypass1, u8 bypass2, + void __iomem *base, + unsigned long flags); enum imx_pllv3_type { IMX_PLLV3_GENERIC, |