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| author | Michael Trimarchi <michael@amarulasolutions.com> | 2015-11-15 11:38:04 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2015-11-25 13:20:18 +0800 |
| commit | 2e133f61882baefaf89dc79c56a7975d80360ef4 (patch) | |
| tree | c62ef73bd5bb73419971f199959c58f1baced96a /drivers/clk/imx | |
| parent | 4824b61c666831e1051530c7f0ff68b0ae6c2511 (diff) | |
| download | linux-2e133f61882baefaf89dc79c56a7975d80360ef4.tar.gz linux-2e133f61882baefaf89dc79c56a7975d80360ef4.tar.bz2 linux-2e133f61882baefaf89dc79c56a7975d80360ef4.zip | |
clk: imx: clk-imx6q: Let OSC to be routed to anaclk2/2b
OSC can be used as USB hub source clock. An example we can route to
CLK2_P imx6 pin.
This show a usage example:
[...]
usb_hub: usb-hub {
compatible = "smsc,usb3503a";
clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
clock-names = "refclk";
};
};
[...]
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
};
/sys/kernel/debug/clk/clk_summary
osc 5 5 24000000 0 0
[...]
lvds2_sel 1 1 24000000 0 0
lvds2_gate 1 1 24000000 0 0
[...]
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'drivers/clk/imx')
| -rw-r--r-- | drivers/clk/imx/clk-imx6q.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index c1935081d34a..f0efc6feeec2 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -70,7 +70,8 @@ static const char *cko_sels[] = { "cko1", "cko2", }; static const char *lvds_sels[] = { "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", - "pcie_ref_125m", "sata_ref_100m", + "pcie_ref_125m", "sata_ref_100m", "usbphy1", "usbphy2", + "dummy", "dummy", "dummy", "dummy", "osc", }; static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", }; static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; |