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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2022-12-25 22:26:32 +0100 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2023-01-13 15:14:12 +0100 |
| commit | 716592fdb5e255a1b9dcb444822c9c1f9a1e248c (patch) | |
| tree | e63f7b30ec3c3138418aacddff2b4e612f3e8b67 /drivers/clk/meson | |
| parent | 9ac323943f7a4c5e5b7c5d4bd6c8225f62b94c43 (diff) | |
| download | linux-716592fdb5e255a1b9dcb444822c9c1f9a1e248c.tar.gz linux-716592fdb5e255a1b9dcb444822c9c1f9a1e248c.tar.bz2 linux-716592fdb5e255a1b9dcb444822c9c1f9a1e248c.zip | |
clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate
clk_ops.round_rate will be removed at some point. It's replacement is
.determine_rate. Switch clk-cpu-dyndiv over to use .determine_rate.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20221225212632.2760126-5-martin.blumenstingl@googlemail.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson')
| -rw-r--r-- | drivers/clk/meson/clk-cpu-dyndiv.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/clk/meson/clk-cpu-dyndiv.c b/drivers/clk/meson/clk-cpu-dyndiv.c index 36976927fe82..8778c149d26a 100644 --- a/drivers/clk/meson/clk-cpu-dyndiv.c +++ b/drivers/clk/meson/clk-cpu-dyndiv.c @@ -27,14 +27,13 @@ static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw, NULL, 0, data->div.width); } -static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *prate) +static int meson_clk_cpu_dyndiv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); - return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0); + return divider_determine_rate(hw, req, NULL, data->div.width, 0); } static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate, @@ -63,7 +62,7 @@ static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate, const struct clk_ops meson_clk_cpu_dyndiv_ops = { .recalc_rate = meson_clk_cpu_dyndiv_recalc_rate, - .round_rate = meson_clk_cpu_dyndiv_round_rate, + .determine_rate = meson_clk_cpu_dyndiv_determine_rate, .set_rate = meson_clk_cpu_dyndiv_set_rate, }; EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops); |