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path: root/drivers/clk/meson
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* clk: meson: s4: fix module autoloadingKrzysztof Kozlowski2024-05-032-0/+2
* clk: meson: fix module license to GPL onlyNeil Armstrong2024-04-1018-18/+18
* clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCFNeil Armstrong2024-04-102-20/+57
* clk: meson: add vclk driverNeil Armstrong2024-04-104-0/+197
* clk: meson: pll: print out pll name when unable to lock itDmitry Rokosov2024-03-291-2/+2
* clk: meson: s4: pll: determine maximum register in regmap configDmitry Rokosov2024-03-291-0/+1
* clk: meson: s4: peripherals: determine maximum register in regmap configDmitry Rokosov2024-03-291-0/+1
* clk: meson: a1: pll: determine maximum register in regmap configDmitry Rokosov2024-03-291-0/+1
* clk: meson: a1: peripherals: determine maximum register in regmap configDmitry Rokosov2024-03-291-0/+1
* clk: meson: Add missing clocks to axg_clk_regmapsIgor Prusov2024-02-051-0/+2
* clk: meson: g12a: add CSI & ISP gates clocksNeil Armstrong2023-11-241-0/+9
* clk: meson: g12a: add MIPI ISP clocksNeil Armstrong2023-11-242-0/+67
* clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocksNeil Armstrong2023-11-241-0/+40
* clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILSArnd Bergmann2023-10-231-0/+2
* clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controllerYu Tu2023-09-274-0/+3881
* clk: meson: S4: add support for Amlogic S4 SoC PLL clock driverYu Tu2023-09-274-0/+918
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2023-08-3028-3287/+2727
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| *-. Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...Stephen Boyd2023-08-3028-3279/+2719
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| | | * clk: meson: axg-audio: move bindings include to main driverNeil Armstrong2023-08-082-3/+2
| | | * clk: meson: meson8b: move bindings include to main driverNeil Armstrong2023-08-082-7/+3
| | | * clk: meson: a1: move bindings include to main driverNeil Armstrong2023-08-084-6/+4
| | | * clk: meson: eeclk: move bindings include to main driverNeil Armstrong2023-08-086-9/+6
| | | * clk: meson: aoclk: move bindings include to main driverNeil Armstrong2023-08-086-45/+9
| | | * dt-bindings: clk: axg-audio-clkc: expose all clock idsNeil Armstrong2023-08-081-70/+0
| | | * dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock idsNeil Armstrong2023-08-081-15/+0
| | | * dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock idsNeil Armstrong2023-08-081-63/+0
| | | * dt-bindings: clk: meson8b-clkc: expose all clock idsNeil Armstrong2023-08-081-108/+0
| | | * dt-bindings: clk: g12a-aoclkc: expose all clock idsNeil Armstrong2023-08-081-17/+0
| | | * dt-bindings: clk: g12a-clks: expose all clock idsNeil Armstrong2023-08-081-140/+0
| | | * dt-bindings: clk: axg-clkc: expose all clock idsNeil Armstrong2023-08-081-58/+0
| | | * dt-bindings: clk: gxbb-clkc: expose all clock idsNeil Armstrong2023-08-081-76/+0
| | | * clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKSNeil Armstrong2023-08-083-428/+424
| | | * clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKSNeil Armstrong2023-08-083-658/+660
| | | * clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKSNeil Armstrong2023-08-085-180/+183
| | | * clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong2023-08-089-73/+68
| | | * clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong2023-08-089-1323/+1312
| | | * clk: meson: introduce meson-clkc-utilsNeil Armstrong2023-08-084-0/+48
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| * / clk: Explicitly include correct DT includesRob Herring2023-07-198-8/+8
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* / clk: meson: change usleep_range() to udelay() for atomic contextDmitry Rokosov2023-07-111-2/+2
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* clk: meson: pll: remove unneeded semicolonJiapeng Chong2023-06-151-1/+1
* clk: meson: a1: Staticize rtc clkStephen Boyd2023-06-121-1/+1
* clk: meson: a1: add Amlogic A1 Peripherals clock controller driverDmitry Rokosov2023-05-304-0/+2367
* clk: meson: a1: add Amlogic A1 PLL clock controller driverDmitry Rokosov2023-05-304-0/+414
* clk: meson: introduce new pll power-on sequence for A1 SoC familyDmitry Rokosov2023-05-302-0/+25
* clk: meson: make pll rst bit as optionalDmitry Rokosov2023-05-301-7/+17
* clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rateMartin Blumenstingl2023-01-131-5/+4
* clk: meson: sclk-div: switch from .round_rate to .determine_rateMartin Blumenstingl2023-01-131-5/+6
* clk: meson: dualdiv: switch from .round_rate to .determine_rateMartin Blumenstingl2023-01-131-8/+13
* clk: meson: mpll: Switch from .round_rate to .determine_rateMartin Blumenstingl2023-01-131-7/+13
*-. Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' ...Stephen Boyd2022-12-121-8/+12
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