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| author | Xiu Jianfeng <xiujianfeng@huawei.com> | 2022-11-23 17:12:01 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2022-11-23 14:51:30 +0100 |
| commit | 739a6a6bbdb793bd57938cb24aa5a6df89983546 (patch) | |
| tree | a7d47e1bd73f225de2acad6534b2d4d6af47fc62 /drivers/clk/rockchip | |
| parent | f1c506d152ff235ad621d3c25d061cb16da67214 (diff) | |
| download | linux-739a6a6bbdb793bd57938cb24aa5a6df89983546.tar.gz linux-739a6a6bbdb793bd57938cb24aa5a6df89983546.tar.bz2 linux-739a6a6bbdb793bd57938cb24aa5a6df89983546.zip | |
clk: rockchip: Fix memory leak in rockchip_clk_register_pll()
If clk_register() fails, @pll->rate_table may have allocated memory by
kmemdup(), so it needs to be freed, otherwise will cause memory leak
issue, this patch fixes it.
Fixes: 90c590254051 ("clk: rockchip: add clock type for pll clocks and pll used on rk3066")
Signed-off-by: Xiu Jianfeng <xiujianfeng@huawei.com>
Link: https://lore.kernel.org/r/20221123091201.199819-1-xiujianfeng@huawei.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-pll.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 4b9840994295..2d42eb628926 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1197,6 +1197,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, return mux_clk; err_pll: + kfree(pll->rate_table); clk_unregister(mux_clk); mux_clk = pll_clk; err_mux: |