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| author | Krzysztof Kozlowski <krzk@kernel.org> | 2016-05-28 11:54:30 +0200 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2016-06-02 11:18:16 +0200 |
| commit | 31d3953f823291c9a6b4650ae6706d9a6974bc80 (patch) | |
| tree | e7aa9468c5bb619d0a3e93657b89140733555751 /drivers/clk/samsung/clk-exynos5410.c | |
| parent | 1ebfb67de8f47c5f277f4a59e7f922a6806e54de (diff) | |
| download | linux-31d3953f823291c9a6b4650ae6706d9a6974bc80.tar.gz linux-31d3953f823291c9a6b4650ae6706d9a6974bc80.tar.bz2 linux-31d3953f823291c9a6b4650ae6706d9a6974bc80.zip | |
clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks
Add clocks for I2C, USI (HSI2C) and RTC to the Exynos5410 clock driver.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5410.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5410.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index 8ad8d5ece7fa..6a924f80cfe4 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -159,6 +159,7 @@ static const struct samsung_div_clock exynos5410_div_clks[] __initconst = { static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0), + GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), @@ -187,6 +188,14 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0), GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0), GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0), + GATE(CLK_I2C0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0), + GATE(CLK_I2C1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0), + GATE(CLK_I2C2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0), + GATE(CLK_I2C3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0), + GATE(CLK_USI0, "usi0", "aclk66", GATE_IP_PERIC, 10, 0, 0), + GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0), + GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0), + GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0), GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", |