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author | Chunyan Zhang <chunyan.zhang@spreadtrum.com> | 2017-12-07 20:57:05 +0800 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-12-21 15:00:51 -0800 |
commit | d41f59fd92f2ef73026f55cd356a4ca253f4716a (patch) | |
tree | e0f552c57e2c789e2579c905f67e26827e236e2c /drivers/clk/sprd/common.c | |
parent | 1ded879e12310b1f8f81b1f84e293933a3b69f14 (diff) | |
download | linux-d41f59fd92f2ef73026f55cd356a4ca253f4716a.tar.gz linux-d41f59fd92f2ef73026f55cd356a4ca253f4716a.tar.bz2 linux-d41f59fd92f2ef73026f55cd356a4ca253f4716a.zip |
clk: sprd: Add common infrastructure
Added Spreadtrum's clock driver framework together with common
structures and interface functions.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/sprd/common.c')
-rw-r--r-- | drivers/clk/sprd/common.c | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/drivers/clk/sprd/common.c b/drivers/clk/sprd/common.c new file mode 100644 index 000000000000..e038b0447206 --- /dev/null +++ b/drivers/clk/sprd/common.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Spreadtrum clock infrastructure +// +// Copyright (C) 2017 Spreadtrum, Inc. +// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com> + +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/regmap.h> + +#include "common.h" + +static const struct regmap_config sprdclk_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xffff, + .fast_io = true, +}; + +static void sprd_clk_set_regmap(const struct sprd_clk_desc *desc, + struct regmap *regmap) +{ + int i; + struct sprd_clk_common *cclk; + + for (i = 0; i < desc->num_clk_clks; i++) { + cclk = desc->clk_clks[i]; + if (!cclk) + continue; + + cclk->regmap = regmap; + } +} + +int sprd_clk_regmap_init(struct platform_device *pdev, + const struct sprd_clk_desc *desc) +{ + void __iomem *base; + struct device_node *node = pdev->dev.of_node; + struct regmap *regmap; + + if (of_find_property(node, "sprd,syscon", NULL)) { + regmap = syscon_regmap_lookup_by_phandle(node, "sprd,syscon"); + if (IS_ERR_OR_NULL(regmap)) { + pr_err("%s: failed to get syscon regmap\n", __func__); + return PTR_ERR(regmap); + } + } else { + base = of_iomap(node, 0); + regmap = devm_regmap_init_mmio(&pdev->dev, base, + &sprdclk_regmap_config); + if (IS_ERR_OR_NULL(regmap)) { + pr_err("failed to init regmap\n"); + return PTR_ERR(regmap); + } + } + + sprd_clk_set_regmap(desc, regmap); + + return 0; +} +EXPORT_SYMBOL_GPL(sprd_clk_regmap_init); + +int sprd_clk_probe(struct device *dev, struct clk_hw_onecell_data *clkhw) +{ + int i, ret; + struct clk_hw *hw; + + for (i = 0; i < clkhw->num; i++) { + + hw = clkhw->hws[i]; + + if (!hw) + continue; + + ret = devm_clk_hw_register(dev, hw); + if (ret) { + dev_err(dev, "Couldn't register clock %d - %s\n", + i, hw->init->name); + return ret; + } + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clkhw); + if (ret) + dev_err(dev, "Failed to add clock provider\n"); + + return ret; +} +EXPORT_SYMBOL_GPL(sprd_clk_probe); + +MODULE_LICENSE("GPL v2"); |