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authorAndrea Venturi <ennesimamail.av@gmail.com>2016-03-21 17:10:38 +0100
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-04-22 00:29:21 +0200
commit8f0767611a0ed719caf975d899d8431834ace2d8 (patch)
tree5c5bf867e6b491b5c2e408ab8c9191461e96c68c /drivers/clk/sunxi
parent92a39d9043ba5ff98adb1c31491f00c7bea5466e (diff)
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clk: sunxi: mod1 clock should modify it's parent
add CLK_SET_RATE_PARENT to modify the rate on clk upstream Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi')
-rw-r--r--drivers/clk/sunxi/clk-a10-mod1.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi/clk-a10-mod1.c b/drivers/clk/sunxi/clk-a10-mod1.c
index e9d870de165c..e2819fa09637 100644
--- a/drivers/clk/sunxi/clk-a10-mod1.c
+++ b/drivers/clk/sunxi/clk-a10-mod1.c
@@ -62,7 +62,7 @@ static void __init sun4i_mod1_clk_setup(struct device_node *node)
clk = clk_register_composite(NULL, clk_name, parents, i,
&mux->hw, &clk_mux_ops,
NULL, NULL,
- &gate->hw, &clk_gate_ops, 0);
+ &gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT);
if (IS_ERR(clk))
goto err_free_gate;