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| author | Thierry Reding <treding@nvidia.com> | 2015-04-20 14:34:57 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 12:41:47 +0200 |
| commit | 1ec7032ad517714108cc53a6ee7067276ca21e80 (patch) | |
| tree | e852e5e9f0788c4dc448f0c9fe41c43e533a82f8 /drivers/clk/tegra/Makefile | |
| parent | 07314fc108e195044c074f4b443974b5aaa2d5d7 (diff) | |
| download | linux-1ec7032ad517714108cc53a6ee7067276ca21e80.tar.gz linux-1ec7032ad517714108cc53a6ee7067276ca21e80.tar.bz2 linux-1ec7032ad517714108cc53a6ee7067276ca21e80.zip | |
clk: tegra: Add fixed factor peripheral clock type
Some of the peripheral clocks on Tegra are derived from one of the top-
level PLLs with a fixed factor. Support these clocks by implementing the
->enable() and ->disable() callbacks using the peripheral clock register
banks and the ->recalc_rate() by dividing the parent rate by the fixed
factor.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/Makefile')
| -rw-r--r-- | drivers/clk/tegra/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index 97984c503bbb..33fd0938d79e 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -3,6 +3,7 @@ obj-y += clk-audio-sync.o obj-y += clk-dfll.o obj-y += clk-divider.o obj-y += clk-periph.o +obj-y += clk-periph-fixed.o obj-y += clk-periph-gate.o obj-y += clk-pll.o obj-y += clk-pll-out.o |