diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2018-01-25 16:00:11 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-03-08 15:26:54 +0100 |
| commit | cbfc8d0a85aa72ad66227c69b08904143dc73bbb (patch) | |
| tree | e960966788a66c4f6e9e4fc740d5de4c179b25b6 /drivers/clk/tegra/clk-tegra-periph.c | |
| parent | 89e423c3f14c4a87d124e4a5437dc337b90b6f29 (diff) | |
| download | linux-cbfc8d0a85aa72ad66227c69b08904143dc73bbb.tar.gz linux-cbfc8d0a85aa72ad66227c69b08904143dc73bbb.tar.bz2 linux-cbfc8d0a85aa72ad66227c69b08904143dc73bbb.zip | |
clk: tegra: add fence_delay for clock registers
To ensure writes to clock registers have properly propagated through the
clock control logic and state machines, we need to ensure the writes have
been posted in the registers and wait for 1us after that.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Hector Martin <marcan@marcan.st>
Tested-by: Andre Heider <a.heider@gmail.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra-periph.c')
0 files changed, 0 insertions, 0 deletions