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| author | Bill Huang <bilhuang@nvidia.com> | 2015-06-18 17:28:33 -0400 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-12-17 13:37:55 +0100 |
| commit | 0ef9db6cf24dbb58118818e64198d9a030e4697e (patch) | |
| tree | bb0b0cb78ca6f1c3ae91d3dded430beafbb696ef /drivers/clk/tegra/clk.h | |
| parent | 17e9273a9e00a1fc8a64d6de3c7bb9e5020b1b73 (diff) | |
| download | linux-0ef9db6cf24dbb58118818e64198d9a030e4697e.tar.gz linux-0ef9db6cf24dbb58118818e64198d9a030e4697e.tar.bz2 linux-0ef9db6cf24dbb58118818e64198d9a030e4697e.zip | |
clk: tegra: pll: Add logic for SS
Add some logic for Spread Spectrum control. It is used in conjuncture
with SDM fractional dividers. SSC has to be disabled when we configure
the divider settings.
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 8dac213fa672..4883507c59dc 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -184,6 +184,8 @@ struct tegra_clk_pll; * @sdm_din_mask: Mask of SDM divider bits * @sdm_ctrl_reg: Register offset where SDM enable is * @sdm_ctrl_en_mask: Mask of SDM enable bit + * @ssc_ctrl_reg: Register offset where SSC settings are + * @ssc_ctrl_en_mask: Mask of SSC enable bit * @aux_reg: AUX register offset * @dyn_ramp_reg: Dynamic ramp control register offset * @ext_misc_reg: Miscellaneous control register offsets @@ -262,6 +264,8 @@ struct tegra_clk_pll_params { u32 sdm_din_mask; u32 sdm_ctrl_reg; u32 sdm_ctrl_en_mask; + u32 ssc_ctrl_reg; + u32 ssc_ctrl_en_mask; u32 aux_reg; u32 dyn_ramp_reg; u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT]; |