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authorThierry Reding <treding@nvidia.com>2015-03-26 17:53:01 +0100
committerThierry Reding <treding@nvidia.com>2015-04-10 16:04:22 +0200
commitc1d676cec572544616273d5853cb7cc38fbaa62b (patch)
tree009f67bdeb71c6ea86a503265690f2729b043239 /drivers/clk/tegra
parenta84724a1c3cccd03b4ca1c8aea135095d0a6204e (diff)
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clk: tegra: Use the proper parent for plld_dsi
The current parent, plld_out0, does not exist. The proper name is pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to be more consistent with other clock names. Fixes: b270491eb9a0 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux") Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
-rw-r--r--drivers/clk/tegra/clk-tegra124.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index f1fa29ec7951..11f857cd5f6a 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1113,16 +1113,18 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1, 2);
clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
- clk = clk_register_gate(NULL, "plld_dsi", "plld_out0", 0,
+ clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
- clks[TEGRA124_CLK_PLLD_DSI] = clk;
+ clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;
- clk = tegra_clk_register_periph_gate("dsia", "plld_dsi", 0, clk_base,
- 0, 48, periph_clk_enb_refcnt);
+ clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
+ clk_base, 0, 48,
+ periph_clk_enb_refcnt);
clks[TEGRA124_CLK_DSIA] = clk;
- clk = tegra_clk_register_periph_gate("dsib", "plld_dsi", 0, clk_base,
- 0, 82, periph_clk_enb_refcnt);
+ clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
+ clk_base, 0, 82,
+ periph_clk_enb_refcnt);
clks[TEGRA124_CLK_DSIB] = clk;
/* emc mux */